1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular to a structure of a DRAM (dynamic random access memory) and a method of manufacturing the same.
2. Description of the Related Art
A demand for semiconductor memory devices is rapidly increased owing to wide use of information equipment such as computers. From a functional standpoint, devices having a large scale storage capacity and capable of operating at a high speed are in great demand. Correspondingly, technology has been developed for improving the degree of integration, speed and reliability of the semiconductor memory device.
DRAMs (Dynamic Random Access Memories) are well known as semiconductor memory devices which allow random input and output of storage information. In general, the DRAM is formed of a memory cell array which is a storage region storing a large number of storage information and a peripheral circuitry for controlling an operation of the memory cell array.
FIG. 28 is a block diagram showing structures of a conventional DRAM. Referring to FIG. 28, a DRAM 150 includes memory cell array 151 for storing data signals of storage information, row and column address buffer 152 for externally receiving an address signal which is used for selecting a memory cell forming a unit storage circuit, row and column decoders 153 and 154 for decoding the address signal and thereby designating a memory cell, sense refresh amplifier 155 for amplifying and reading a signal stored in the designated memory cell, data-in and data-out buffers 156 and 157 for input and output of data, and clock generator 158 for generating a clock signal.
The memory cell array 151 which occupies a large area on the semiconductor chip is formed of a plurality of memory cells which are arranged in a matrix form and each are adapted to store the unit storage information. Each memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. The memory of the above structure is called a memory cell of one-transistor/one-capacitor type. Since the memory cell of this type has a simple structure, degree of integration of the memory cell array can be easily increased. By this reason, they are widely used in DRAMs of a large capacity.
The memory cells of the DRAMs are classified into several types in a accordance with structures of capacitors. In a stacked type capacitor memory cell, a major portion of the capacitor is extended up to positions above a gate electrode and a field isolating film for increasing an area of opposed portions of electrodes in the capacitor.
This can increase a capacitor capacitance. The stacked type capacitor having the above feature can ensure a sufficient capacitor capacitance even if elements are miniaturized in accordance with high integration of the semiconductor device. Consequently, the stacked type capacitors have been widely used in accordance with high integration of the semiconductor memory devices.
However, it is difficult to ensure an intended capacitor capacitance in the stacked type capacitor described above, if elements are further miniaturized for forming a DRAM, e.g., of 256 Mbits.
In order to increase the capacitor capacitance, it has been attempted to use a high dielectric film such as PZT (lead zirconate titanate ceramics). FIGS. 29A and 29B show an example of a DRAM in which the high dielectric film such as PZT is used as the dielectric film of capacitor.
Referring to FIGS. 29A and 29B, the DRAM includes a memory cell array and a peripheral circuitry as described above. A structure of the memory cell array of the conventional DRAM will now be described below. In the memory cell array, a p-type semiconductor substrate 201 is provided at its main surface with an element isolating region, at which a field oxide film 202 is formed. Semiconductor substrate 201 is also provided at its main surface with an element forming region, at which transfer gate transistors 204a and 204b are formed.
Transfer gate transistor 204a includes n-type impurity regions 203a and 203b, which are formed at the main surface of semiconductor substrate 201 with a space between each other for forming source/drain regions, and a gate electrode (word line) 207a formed on a channel region between impurity regions 203a and 203b with a gate insulating film 206a therebetween.
Transfer gate transistor 204b includes n-type impurity regions 203b and 203c forming source/drain regions, and a gate electrode 207b formed on a channel region between impurity regions 203b and 203c with a gate insulating film 206b therebetween.
Gate electrodes 207c and 207d of another transfer gate transistor are extended over field oxide film 202. Gate electrodes 207a, 207b, 207c, and 207d are covered with oxide film 209. A buried bit line 210 is formed on impurity region 203b and is electrically connected thereto. Buried bit line 210 is covered with an insulating layer 212.
Insulating layer 212 and oxide films 209 are covered with a first interlayer insulating film 214 having a flattened top surface. First interlayer insulating film 214 is provided with first contact holes 215 located above impurity regions 203a, 203c and 203d.
In contact holes 215 are formed first plug electrodes 216 electrically connected to impurity regions 203a, 2023c and 203d, respectively. Capacitor lower electrodes 217 are formed on first plug electrodes 216 with barrier layers 229 interposed therebetween and are electrically connected thereto. Capacitor lower electrodes 217 may be formed of platinum (Pt). Barrier layers 229 prevent diffusion between the material of capacitor lower electrode 217 and the material of first plug electrode 216.
Capacitor lower electrodes 217 are covered with a capacitor dielectric film 218, which is formed of high dielectric material such as SrTiO.sub.3. Capacitor dielectric film 218 is covered with a capacitor upper electrode 219, which is formed of material such as platinum (Pt).
Capacitor upper electrode 219 is covered with a second interlayer insulating film 220 having a flattened top surface. A distance D between the top surface of second interlayer insulating film 220 and the main surface of semiconductor substrate 201 is about 1.7 .mu.m.
First aluminum interconnection layers 221 are formed on second interlayer insulating film 220 with a space between each other. First aluminum interconnection layers 221 are covered with a protective film 222, on which second aluminum interconnection layer 223 is formed. Capacitor lower electrodes 217, capacitor dielectric film 218 and capacitor upper electrode 219 form a capacitor 224.
Now, a structure of the peripheral circuitry of the conventional DRAM will be described below. In the peripheral circuitry shown in FIG. 29B, field oxide films 202 which are spaced from each other are formed at the element isolating regions in the main surface of p-type semiconductor substrate 201. A MOS transistor 205 is formed at the element forming region in the main surface of semiconductor substrate 210.
MOS transistor 203 includes n-type impurity regions 203f and 203g forming source/drain regions, and a gate electrode 208 formed on a channel region between impurity regions 203f and 203g with a gate insulating film 206c therebetween. An impurity region 203e of another transistor is formed at the element forming region in the main surface of semiconductor substrate 201.
A polysilicon pad 211a is formed on impurity region 203f and is electrically connected thereof. A polysilicon pad 211b is formed on impurity region 203g and is electrically connected thereto. Polysilicon pad 211a is covered with an insulating layer 213. Gate electrode 208 is covered with an oxide film 209a.
A first interlayer insulating film 214a is formed over the main surface of semiconductor substrate 201. A second interlayer insulating film 220a is formed on first interlayer insulating film 214a. Second interlayer insulating film 220a is formed at the peripheral circuitry when second interlayer insulating film 220 is formed at the memory cell array. Second interlayer insulating film 220a contributes to ensure insulation between first aluminum interconnection layer 221a, which will be described later, and conductive layer formed on semiconductor substrate 210. However, even if second interlayer insulating 220a were eliminated, insulation between first aluminum interconnection layer 221a and the conductive layers on semiconductor substrate 210 would be ensured by first interlayer insulating film 214a.
There are formed second contact holes 215a penetrating first and second interlayer insulating films 214a and 220a. A depth D2 of second contact holes 215a varies depending on a position of them, and is in a range from about 0.8 .mu.m to about 2.0 .mu.m. The depth specifically varies in accordance with variation of film thicknesses of first and second interlayer insulating films 214a and 220a due to irregular or stepped shape of the bases of them.
Second plug electrodes 216a made of, e.g., polysilicon are formed in second contact holes 215a. First aluminum interconnection layers 221a are formed on second plug electrodes 216a. First aluminum interconnection layers 221a are covered with a protection layer 222a, on which second aluminum interconnection layer 223a is formed.
A method manufacturing the conventional DRAM having the above structure will be described below. FIGS. 30A and 30B to 36A and 36B are fragmentary cross sections showing 1st to 7th steps in the process of manufacturing the conventional DRAM.
Referring first FIGS. 30A and 30B, field oxide films 202 are formed at the elements isolating regions on the main surface of semiconductor substrate 201, e.g., by a LOCOS (Local Oxidation Of Silicon) method. Then, gate insulating films 206a, 206b and 206c are formed, e.g., by a thermal oxidation method. In the memory cell array, gate electrodes (word lines) 207a, 207b, 207c and 207d are selectively formed on gate insulating films 206a and 206b as well as field oxide films 202. At the same time, gate electrode 208 is formed on gate insulating film 206c in the peripheral circuitry.
Then, impurity is implanted into the main surface of semiconductor substrate 201 using gate electrodes 207a, 207b and 208 and field oxide films 202 as a mask. Thereby, impurity regions 203a, 203b, 203c and 203d are formed in the memory cell array, and impurity regions 203e, 203f and 203g are formed in the peripheral circuitry.
Then, oxide films 209 and 209a are formed over gate electrodes 207a, 207b, 207c and 208. A polysilicon layer is formed over the whole main surface of semiconductor substrate 201, and then is patterned into a predetermined configuration. Thereby, buried bit line 210, which is electrically connected to impurity region 203b, is formed on impurity region 203b in the memory cell array. At the same time, polysilicon pad 211a electrically connected to impurity region 203f is formed on impurity region 203f in the peripheral circuitry.
Insulating layers 212 and 213 are formed to cover buried bit line 210 and polysilicon pad 211a. Then, a polysilicon layer is deposited over the whole main surface of semiconductor substrate 201. The polysilicon layer is patterned to form polysilicon pad 211b on impurity region 203g electrical connected thereto.
Then, a CVD method or the like is used to form first interlayer insulating films 214 and 214a made of e.g., BPSG (Boro-Phospho Silicate Glass) on the whole main surface of semiconductor substrate 201. Flattening processing is effected on first interlayer insulating films 214 and 214a.
Referring to FIGS. 31A and 31B, first contact holes 215 reaching the surfaces of impurity regions 203a, 203c and 203d are formed at first interlayer insulating film 214 in the memory cell array. A polysilicon layer (not shown) filling first contact holes 215 is formed over first interlayer insulating film 214 to fill first contact holes 215. Etchback is effected on the polysilicon layer to form first plug electrodes 216 made of polysilicon in first contact holes 215.
Referring to FIGS. 32A and 32B, barrier layers 229 made of TiN and capacitor lower electrodes 217 made of, e.g., platinum (Pt) are formed on plugs 216 by a sputtering method or the like. Capacitor dielectric film 218 made of high dielectric material is formed to cover capacitor lower electrode 217 by a sputtering method or the like.
Capacitor dielectric film 218 may be made of tantalum oxide (TaO.sub.2), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium titanate (STO) or barium titanate (BTO).
Capacitor upper electrode 219 made of, e.g., platinum (Pt) is formed on capacitor dielectric film 218 by a sputtering method or the like. Thereby, capacitors 224 each including capacitor lower electrode 217, capacitor dielectric film 218 and capacitor upper electrode 219 are formed on first interlayer insulating film 214.
Referring to FIGS. 33A and 33B, second interlayer insulating film 220 made of, e.g., a BPSG film is formed on capacitor upper electrode 219 in the memory cell array by a CVD method or the like. At the same time, second interlayer insulating film 220a is formed on first interlayer insulating film 214 in the peripheral circuitry. Flattening processing is effected on second interlayer insulating films 220 and 220a.
Referring to FIGS. 34A and 34B, second contact holes 215a penetrating first and second interlayer insulating films 214a and 220a are formed in the peripheral circuitry. Depth D2 of second contact holes 215 thus formed in the peripheral circuitry varies within a large range from about 0.8 .mu.m to about 2.0 .mu.m.
Second contact holes 215a have depth D2 of various values due to the fact that film thicknesses of first and second interlayer insulating films 214a and 220a varies depending on their position on semiconductor substrate 201 due to irregular or stepped shaped of their bases.
Referring now FIGS 35A and 35B, second plug electrodes 216a made of, e.g., polysilicon are formed in second contact holes 215a formed in the peripheral circuitry. Second plug electrodes 216a are required due to the fact that second contact holes 215a have the depth of various values from about 0.8 .mu.m to about 2.0 .mu.m as described above.
Referring to FIGS 36A and 36B, first aluminum interconnection layers 221 which are spaced from each other are formed on second interlayer insulating film 220 in the memory cell array by sputtering method or the like. At the same time, first aluminum interconnection layers 221a are formed on the top surfaces of second plug electrodes 216a in the peripheral circuitry.
Thereafter, protective films 222 and 222a are formed to cover first aluminum interconnection layers 221 and 221a, and second aluminum interconnection layers 223 and 223a are formed over protective films 222 and 222a, respectively. Through the steps described above, the conventional DRAM shown in FIGS. 29A and 29B is completed.
The conventional DRAM described above, however, has problems which will be described below with reference to FIGS. 37 and 38. FIG. 37 shows a first problem of the convention DRAM, and is a fragmentary cross section of the peripheral circuitry at a 5th step in the process of manufacturing the conventional DRAM. FIG. 38 shows a third problem of the conventional DRAM, and is a fragmentary cross section of the peripheral circuitry at a 7th step in the process of manufacturing the conventional DRAM.
The first problem of the conventional DRAM will now be described below with reference to FIG. 37. As shown in FIG. 37, depth D2 of second contact holes 215a formed at the peripheral circuitry in the conventional DRAM varies within a range from a small value less than about 1 .mu.m to large values of about 1.8 .mu.m to about 2.0 .mu.m. Thus, depth D2 of second contact holes 215a varies to a relatively large extent.
Meanwhile, second contact holes 215a generally have an open width W of a substantially constant value from about 0.6 .mu.m to about 0.8 .mu.m. Therefore, the aspect ratio of second contact holes 215a varies within a range from a small value of about 1 to a large value from 2 to 3 or more. Thus, the aspect ratio varies to a relatively large extent.
In accordance with higher integration, however, open width W of second contact holes 215a is reduced. This further increases the value of aspect ratio of contact holes 215a. In other words, in accordance with higher integration, the value of aspect ration further increases. As a result, higher integration makes it extremely difficult to form second contact holes 215a in the peripheral circuitry.
Now, a second problem of the conventional DRAM will be described below. This problem is caused by the above increase of aspect ration of second contact holes 215a in accordance with higher integration.
The increase of aspect ratio of second contact holes 215a in accordance with the integration causes the following necessity. Second contact holes 215a must be filled, e.g., with second plug electrodes 216a so as to make contact between first aluminum interconnection layers 221a and impurity regions 203e, 203f and 203g.
More specifically, extra steps must be employed for forming second plug electrodes 216a within second contact holes 215a so as to make contact between first aluminum interconnection layer 221a and impurity regions 203e, 203f and 203g in the peripheral circuitry. This increases a manufacturing cost and complicates the manufacturing process.
The third problem of the conventional DRAM will be described below with reference to FIG. 38. As already described, open width W of second contact holes 215a in the peripheral circuitry decreases in accordance with higher integration as shown in FIG. 38. A plan width W1 of first aluminum interconnection layers 221a formed on second contact holes 215a also decreases.
This reduces a maximum allowable magnitude of dislocation of the mask used for pattering first aluminum interconnection layers 221a. As a result, the structure of conventional DRAM causes the problem that formation of first aluminum interconnection layers 221a becomes difficult in accordance with higher integration.